GSBUSCFG1

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Interpret as GSBUSCFG1

PIPETRANSLIMIT=Val_0x0

Description

Global SoC Bus Configuration Register 1

Fields

PIPETRANSLIMIT

AXI pipelined transfers burst request limit. This bit field controls the number of outstanding pipelined transfer requests the AXI master pushes to the AXI slave. When the AXI master reaches this limit, it does not make any more requests on the AXI ARADDR and AWADDR buses until the associated data phases complete. This bit field is encoded as follows:

0 (Val_0x0): 1 request

1 (Val_0x1): 2 requests

2 (Val_0x2): 3 requests

3 (Val_0x3): 4 requests

15 (Val_0xF): 16 requests

EN1KPAGE

1KB page boundary. By default (this bit is disabled) the AXI breaks transfers at the 4KB page boundary. When this bit is enabled, the AXI master (DMA data) breaks transfers at the 1KB page boundary.

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